IC Design (Netlist to GDSII) | Print |  E-mail
engineer.gifDCD has expertise in physical design for multi-million gates in 90nm and below, with one or more of the following characteristics:
  • Hierarchical or flat
  • Multi-voltage design
  • Flip chip or wirebond
  • Multi-project wafer or production chip


The DCD services offering includes:
  • Physical synthesis
  • Floorplanning
  • Package selection
  • Virtual prototyping
  • Power planning and analysis, IR-drop estimation
  • Clock tree synthesis
  • Place & Route (P&R)
  • Physical verification, signal integrity
  • Extraction, timing analysis
  • DFM yield & reliability issues
  • GDSII Tape-out to Wafer Fab
  • IP quality check and IP integration
  • Library quality checks
  • Interface with the vendor


DCD relies on the proven Synopsys EDA tools like Jupiter, ASTRO, IC Compiler, PT-SI to achieve:
  • The design goal’s timing, area and power
  • Predictable and repeatable results
  • Fast turn around time
  • High quality results using Synopsys PILOT design flow